Preface: Intelligent sensor technology is a rapidly developing modern sensor technology, integrating multiple disciplines such as micromechanics and microelectronics, computer technology, network and communication technology, signal processing technology, circuits and systems, sensing technology, neural network technology, information fusion technology, wavelet transform theory, genetic theory, and fuzzy theory. Intelligent functions in intelligent sensors, such as digital signal output, information storage and memory, logical judgment, decision-making, self-testing, self-calibration, and self-compensation, are all based on microprocessors. Microprocessor-based sensors have evolved from simple digitization and information processing to modern intelligent sensors with increasingly sophisticated technologies and theories, including network communication, neural networks, fuzzy theory, genetic theory, wavelet transform theory, and multi-sensor information fusion. Their microprocessor hardware has also evolved from single-CPU structures to multi-CPU and even hybrid structures combining DSP, ASIC, and MCU. However, microprocessors have inherent and insurmountable shortcomings in reliability, power consumption, and function reuse, hindering the further development of intelligent sensors. The shift from System-on-Chip (SoC) to System-on-Chip (SOC) has become an inevitable trend. SOC implements functions previously implemented in software using hardware. Compared to general MCUs, it has a series of advantages such as high reliability, low price, high speed, small size, function reuse, and good security. Traditional SoC design is based on ultra-deep submicron IC design technology, which has the complexity of integrated circuit ASIC design. With the development of SoC platforms and EDA technology, and the promotion of the new IP economic model, SoC application design is increasingly shifting from traditional silicon chip design to the use of large-scale programmable FPGA chip design. FPGA-based SoC design has the characteristics of short development cycle, standardized development tools and languages, and design and device independence, making it as easy as using a microcontroller. A large number of reports on the successful application of FPGAs are in the fields of image processing and power systems. Its application in the field of intelligent sensors is still in the development and research stage. The few applications in sensors are limited to using it as one or several independent functional modules, such as communication modules and self-compensation modules, which do not have the role and function of a system and cannot truly become a system-on-a-chip (SoC). This paper proposes a smart sensor SOC/IP design integrating functional modules such as data acquisition, compensation and correction, data processing, data communication, task scheduling, human-machine interface, and IP function reuse, and its implementation method based on FPGA and ARM7 microprocessor chips. SOC/IP Concept and Smart Sensor SOC Design Method : SOC: System on Chip, refers to a system built on a single chip. IP: Intellectual Property. Traditional smart sensor design methods are based on functional design. SOC design, however, is based on function reuse and construction, using several macro-modules on a chip to build complex systems. These developed macro-modules are general-purpose IP cores. Reusing IP cores can reduce product design complexity and shorten time-to-market. Complete smart sensor systems can be assembled using SOC/IP chips. The sensing parameters of smart sensors may be diverse. However, in terms of functional module composition, it mainly includes functional units such as data acquisition modules, compensation and correction modules, data processing modules, data network communication modules, human-machine interface, and task management and scheduling modules. Therefore, the design process of an IP-based intelligent sensor SOC is as follows: First, correctly establish a general module model of the intelligent sensor; then, rationally divide the functional specifications of each module and formulate the interface protocols and standards between each module; next, design a series of general-purpose IP cores; finally, integrate the required general-purpose IP cores to form a complete intelligent sensor system. Intelligent Sensor IP Core Design and SOC Construction Intelligent sensors involve various functions such as data acquisition, signal processing (programmable amplification, linearization, signal filtering, signal compensation, artificial neural networks, genetic theory, multi-sensor fusion, fuzzy theory, etc.), data communication, human-machine interface, and task scheduling. In IP core design and SOC construction, to simplify the work and reduce complexity, we choose two SOC design methods: FPGA-based IP cores and ARM7TDMI-SCPU-based IP cores. The FPGA-based IP cores mainly complete the data acquisition and signal processing modules, while the ARM7-based IP cores complete data communication, human-machine interface, and task scheduling. Data Acquisition Traditional sensor signal digitization mostly adopts schemes such as VFC, serial A/D, and parallel A/D. Each solution can be designed as a corresponding IP core. Although some people have used FPGAs for data acquisition, these are application-specific designs rather than general-purpose IP cores. We introduce a parallel A/D interface IP core design using the MAX125. The MAX125 is an 8-channel, 14-bit parallel A/D chip. In the FPGA A/D IP core design, the signals provided to the MAX125 include timing signals for starting the conversion and completing the conversion, as well as data signals for reading the conversion result and storing it in the FPGA chip's internal RAM. We have successfully developed this A/D IP core and it has been used successfully. Signal Processing Signal processing is one of the main components of intelligent sensors. It typically includes linearization, filtering, various compensation methods, artificial neural networks, fuzzy theory, genetic algorithms, and multi-sensor fusion. In filtering, in addition to the conventional FFT and DFT, wavelet transform has emerged in recent years. Due to the speed advantage of chips, how to achieve a generalized design for various signal processing IP cores has become crucial for the design of related signal processing algorithm IP cores. For example, in the linearization processing design, we have designed the linearization algorithms for various sensors into a general-purpose linearization IP core. During task invocation, the appropriate algorithm IP core is selected based on the linearization algorithm requirements of different sensor types for actual use. Data Communication Setting up the data communication interface is primarily to consider that the chip can also form a more complex measurement and control system with an external CPU or network. To facilitate chip design and save chip resources, we chose the philIPs LPC2106 chip based on ARM7 for the communication IP core design. It can implement a series of different communication interfaces (such as CAN, Ethernet, TCP/IP, RS232/485, I2C, SPI) and different communication protocols using a single general-purpose microprocessor. Through connection with a host computer and various networks, functions such as remote telemetry and network-based remote intelligent measurement nodes are realized. The main task of the communication IP core design is the design of the communication protocol algorithm. Since most interfaces can be provided by the ARM7-based microprocessor, little work is required. Human-Machine Interface and Task Scheduling The human-machine interface and task scheduling IP core is also designed using an ARM7 microprocessor. The human-machine interface mainly designs a keyboard interface and display interfaces such as LCD/LED/CRT. Implementing this using the powerful GPIO functionality of the ARM7 is not difficult. The task scheduling IP mainly includes data acquisition scheduling, signal processing scheduling, data communication scheduling, and human-machine interface scheduling. We use the publicly available embedded operating system μC/OS-Ⅱ version 2.52 as a base and port it to the LPC2106 ARM microprocessor. Various application software is developed based on the μC/OS-Ⅱ embedded operating system to complete the various task scheduling and configuration tasks required by the intelligent sensor. Application Example With the basic IP core, we can construct various required intelligent sensor systems as needed by configuring the IP core (under the scheduling of the embedded operating system μC/OS-Ⅱ). Figure 1 shows a SOC design example for an intelligent sensor used for thermocouple temperature measurement. All algorithm IP modules are loaded onto the ALTERA APEX20K multi-chip FPGA to complete functions such as temperature signal acquisition, A/D conversion, low-end compensation, linearization, and programmable amplification. The chip's overall external pins include data and control lines for the A/D interface, data and control lines for the microprocessor interface, and control lines for the programmable amplifier. The microprocessor used is the Philips LPC2106 chip with an ARM IP core. It performs communication functions, real-time clock functions, human-machine interface functions, and task scheduling functions. Communication IPs include I2C bus, RS232/RS485 bus, CAN bus, TCP/IP protocol, and Ethernet. [IMG=IP-based Smart Sensor SOC Design]/uploadpic/THESIS/2007/12/20071211110847624688.jpg[/IMG] Figure 1 shows the IP-based smart sensor SOC design. Figure 2 is a block diagram of the thermocouple smart sensor based on the above system chips. Its core consists of two SOCs: the FPGA SOC uses the APEX20K, and the MCU SOC uses the ARM7 TDMI-S microprocessor with an ARM IP core. The prototype of this smart sensor has been completed. The FPGA chip underwent hardware simulation testing, and its A/D sampling, linearization algorithm, cold junction temperature compensation, and multi-sensor fusion functions and algorithms have all been experimentally verified. The MCU SOC, running at a 48MHz system clock, passed experiments on communication, human-machine interface, real-time calendar clock, and task scheduling management functions, verifying the feasibility of the design. [IMG=Block diagram of a thermocouple intelligent sensor based on an SOC chip]/uploadpic/THESIS/2007/12/20071211110854455497.jpg[/IMG] Figure 2 Block diagram of a thermocouple intelligent sensor based on an SOC chip Conclusion This paper introduces the design method of intelligent sensor IP/SOC through examples. Based on the design of a general-purpose intelligent sensor IP core, through IP reuse, only the data and task calling modules need to be changed or reset to design an SOC system applicable to other types of intelligent sensors. Due to limitations in SOC development and EDA design tools, designing intelligent sensor SOCs/IPs based on FPGAs and MCUs, and focusing on practical system applications, is a research approach that aligns with current SOC design practices and my country's actual situation. To improve the design capabilities of intelligent sensor SOCs/IPs, special attention must be paid to summarizing the following aspects: ① EDA tools: including development tools, design tools, analysis tools, and verification tools. ② HDL language tools: fully utilize the advantages of HDL language structure, adopt a top-down modular design, and emphasize detailed configuration and interface standardization. ③ IP resources: on the one hand, this refers to fully utilizing existing general-purpose IP resources and standards, such as interfaces, specifications, and testability, as well as the IP core resources of ARM, the company with the largest market share in the world. On the other hand, it refers to summarizing and improving the IP cores of intelligent sensors themselves. The field-programmable nature of FPGAs makes SOC/IP-based intelligent sensor design more flexible, and the parallel processing capability of each IP module enables the implementation of complex algorithms that were previously impossible with a single CPU, such as sensor calibration algorithms, compensation algorithms, neural network sensing algorithms, fuzzy sensing algorithms, and multi-sensor fusion algorithms requiring high-speed data processing. This can further improve measurement accuracy, measurement range, and measurement content. At the same time, implementing functions previously only available in software using hardware can solve the problem of program crashes caused by interference, greatly improving the reliability of the intelligent sensor system.