The space age has not only promoted the rapid development of launch vehicle technology, satellite technology and deep space exploration technology, but also transformed the Earth-based Internet into a space-based network, extending to Mars, 120 million kilometers away, and promoted the rapid development of aerospace microelectronics application technologies such as space-based embedded image processing technology. Embedded Image Processing Technology The characteristics of space-based embedded image processing technology are: first, embeddability, that is, high requirements for size, weight and power consumption; second, complexity, requiring the processing of gigabyte-level pixel frames; third, reliability, requiring adaptation to harsh working environments and long lifespan; fourth, real-time performance, generally requiring second-level computing time. In order to achieve these characteristics, it is necessary to study the functions, structure and physical implementation of aerospace embedded computers. (1) Unified Architecture Model In order to simultaneously meet the requirements of improving chip integration and shortening the design cycle, design platform technology based on IP cores and co-design methods from function to architecture have been developed. Because non-control-flow computer architectures are complex and inefficient, current computer architectures all adopt control-flow architectures. According to our proposed computer architecture classification model, control-flow architectures can be divided into three categories: First, instruction-flow-based architectures, represented by microprocessors. Based on Flynn's classification using the logical concepts of instruction flow and data flow, there are four architectures: SISD, SIMD, MISD, and MIMD. Second, data-flow-based architectures, represented by ASIC (e.g., systolic array) circuits. Because they only have the concept of data flow, there are only SD and MD categories. Although ASIC circuits are highly efficient, statically programmable FPGA circuits emerged to overcome the lack of flexibility compared to processors. Third, configuration-stream-based architectures, often called reconfigurable architectures, or dynamically programmable circuits, include four categories: SCSD, SCMD, MCSD, and MCMD. These logically categorized architectures can be combined, resulting in 1023 possible schemes. In terms of specific implementation, the solutions are even more numerous; for example, the instruction sets of processors from different manufacturers are different. The co-design of functionality and architecture is accomplished through the mapping from functionality to architecture. To ensure the efficiency and uniformity of this mapping, a unified architecture model is proposed, unifying the architecture in three aspects: First, a Unified _ISA model is proposed, as shown in Figure 1, which unifies the above three architectures in terms of instruction sets; second, an intermediate mapping language is proposed, which compromises between high-level languages ​​and assembly languages, unifying the compatibility and readability of high-level languages ​​with the program efficiency and mapping directness of assembly languages; third, through programming in the intermediate mapping language, the design of software components and hardware components can be unified. Figure 1 shows the logical concept diagram of the Unified _ISA model. Specifically, for the instruction flow architecture, the instruction subsets of the four architectures SISD, SIMD, MISD, and MIMD are unified into the instruction set of the SISD architecture. For the data flow and instruction flow architectures, corresponding instructions are added to unify them into the instruction set of the SISD architecture. In other words, the four MPP units in Figure 1—SIMD, MIMD, ASIC, and RC Device—can all be described by software components. These software components can be executed directly on SIMD or MIMD architectures, or can be automatically mapped to ASIC or RC device circuits. (2) Virtual parallel computing array Due to the need for G-level pixel frame remote sensing image processing, MPP parallel computing arrays have been developed because image frames are always two-dimensional, and the corresponding processing element arrays are also two-dimensional, as shown in Figure 2. Although the chip integration is already very high, it is still not possible to develop an array of G-level pixel frames with G processing elements on a single chip. Currently, only arrays with millions of processing elements are completed using WSI technology. Therefore, virtual processing element array technology can only be used to solve the convenience of MPP program design and the readability of the program itself. In other words, MPP image processing programs are designed according to virtual parallel computing arrays. That is, when designing MPP programs, it is always assumed that the values ​​of M and N of the grid array in Figure 2 are equal to the dimension of the image frame, while the actual size of the processing element array m×n is much smaller than M×N. MPP programs are executed by automatically mapping to the actual processing element array. In view of the characteristics of image processing algorithms, the MPP computing array for image processing is usually designed according to the SIMD architecture. The corresponding design problems include: handling the position representation and position selection of the PE, using PIM design to solve the bandwidth problem between the image processor and the image memory, and the parallel resampling problem. Figure 2 M×N virtual processing element array (3) Bionic physical implementation technology The desire for the mysteries of the universe and the brain has inspired human space travel and human body travel, enabling embedded computing technology to develop from traditional computing mode to autonomous computing mode and move towards natural computing mode. The chip implementation technology of traditional computing has now developed from single-function chips to a new stage of multi-functional SoC chips. The software implementation technology has evolved from structured programming to object-oriented programming, to component-based programming and to agent-based programming. In August 1956, John McCarthy first proposed the concept of artificial intelligence (AI). At that time, he said, "The era of machines thinking will come in less than 20 years." However, artificial intelligence is still in its early stages and has only achieved success in "cognitive science" and expert systems, which illustrates the difficulty of artificial intelligence. It is estimated that from 200X to 201X, we will enter the 30nm nanoelectronic era, where biomimetic technologies for autonomous computing, such as autonomous robot movement, gravity-based walking and airflow-based sound generation, and fisheye lens photography, will be further refined. Current research on biomimetic technologies for autonomous computing mainly focuses on utilizing the reasoning capabilities of fuzzy logic, the learning capabilities of neural networks, and the optimization capabilities of gene computing. The real challenge lies in changing and redefining the nature of computing hardware. In many ways, the human body is a highly efficient computer. The nervous system transmits signals between the brain and nerve centers throughout the body through the movement of sodium (Na) and potassium (K) ions, which are then interpreted and processed by the brain to control bodily activities. It is estimated that from 201X to 20XX, we will enter the 10nm nanoelectronic era, promoting the development of biomimetic technologies for natural computing, such as self-assembly technology for quantum computing, DNA technology for chemical computing, and neuron technology for fault-tolerant computing. In particular, molecular self-assembly technology has already achieved practical results such as laboratory-scale machine tools (ALMs). Conclusion In summary, we proposed a unified architecture model from a functional perspective, designed a processing element array that effectively supports virtual parallel computing programming from a structural perspective, and investigated a design platform that supports self-assembly technology from a physical implementation perspective. In conclusion, SoC chips, nanofabrication, and self-assembly technologies will further promote the development of embedded image processing technology in the aerospace era.