Abstract: A compact image acquisition and processing system was implemented using an ARM7 (LPC2210) and a CMOS image sensor (OV7620). By rationally utilizing the LPC2210's data bus operation mode, the interference of the OV7620 on the system data bus was effectively eliminated. SCCB control, image data acquisition, processing, and transmission are all completed by a single LPC2210, making it particularly suitable for embedded applications with strict requirements on power consumption and size. Keywords: Image data, image acquisition system, ARM, interrupt response, instruction cycle, stop condition, bitmap file, DMA controller, BMP bitmap, QVGA. The OV7620 is a CMOS image sensor widely used in products such as webcams and camera phones. A common design approach for image acquisition systems using it is to pair the OV7620 with an OV511+ or CPLD/FPGA. Image data acquired by the OV511+ or CPLD/FPGA is output to a PC or MCU (ARM, DSP, etc.) via a USB bus or dual-port RAM for further processing. The image acquisition system designed in this paper implements the functions of OV7620, including control, timing synchronization, data acquisition, and processing, using only one ARM chip. The system structure is compact and practical. 1. Hardware Structure OV7620 is a CMOS color/black and white image sensor. It supports both continuous and interlaced scanning modes, and VGA and QVGA image formats; the maximum pixel count is 664492, and the frame rate is 30fp8; the data formats include YUV, YCrCb, and RGB, which can meet the requirements of general image acquisition systems. The OV7620's internal programmable function registers have power-on mode and SCCB programming mode. This system adopts SCCB programming mode, continuous scanning, and 16-bit RGB data output. The system hardware structure block diagram is shown in Figure 1. The ARM chip selected is the LPC2210 with an ARM7TDMI core. The SCCB bus protocol is simulated through the LPC2210's GPIO to control the OV7620's function registers. The image output synchronization signals VSYNC, HSYNC, and PCLK of the OV7620 are introduced through the three interrupt pins of the LPC2210 to synchronize image data output via interrupts. The 16-bit parallel data output from the OV7620's YUV channel is accessed through the high 16-bit data lines of the LPC2210. The SST39VF160 and IS61LV25616AL are extended Flash and SRAM, respectively used as program memory and data memory. 2 Implementation Details 2.1 Functional Control of OV7620 The OV7620 is controlled using the SCCB (Serial Camera Control Bus) protocol. SCCB is a simplified I2C protocol. S10-1 is the serial clock input line, and S10-0 is the serial bidirectional data line, which are equivalent to SCL and SDA in the I2C protocol, respectively. The bus timing of SCCB is basically the same as that of I2C. Its response signal ACK is called the 9th bit of a transmission unit and is divided into Don't care and NA. The "Don't care" bit is generated by the slave device; the "NA" bit is generated by the master device. Since SCCB does not support multi-byte read/write operations, the "NA" bit must be high. Furthermore, SCCB does not have a repeat start concept; therefore, during an SCCB read cycle, after the master device sends the on-chip register address, it must send a bus stop condition. Otherwise, the slave device will not generate a "Don't care" response signal when sending a read command. Due to some subtle differences between I2C and SCCB, GPIO is used to simulate the SCCB bus. The pin connected to SCL is always set to output mode, while the pin connected to SDA dynamically changes its input/output mode during data transmission by setting the IODIR value. SCCB write cycles directly use the I2C bus protocol's write cycle timing; while SCCB read cycles add a bus stop condition. The addresses of the OV7620 function registers are 0x00 to 0x7C (many of which are reserved registers). By setting the corresponding registers, the OV7620 can operate in different modes. For example, to set the OV7620 to continuous scanning and 16-bit RGB raw data output mode, the following settings are required: I2CSendByte() is a register write function. Its first parameter, OV7620, is the macro-defined chip address 0x42, the second parameter is the on-chip register address, and the third parameter is the corresponding register setting value. 2.2 OV7620 Clock Synchronization The OV7620 has four synchronization signals: VSYNC (vertical synchronization signal), FODD (odd field synchronization signal), HSYNC (horizontal synchronization signal), and PCLK (pixel synchronization signal). When using continuous scanning mode, only VSYNC, HSYNC, and PCLK synchronization signals are used, as shown in Figure 1. To detect the effective size of the OV7620 scanning window, the HREF horizontal reference signal is also introduced. The three external interrupt pins of the LPC2210 are used as inputs to the three synchronization signals, and the corresponding interrupt service routines are Vsync_IRQ(), Hsync_IRQ(), and Pclk_IRQ(), respectively. A two-dimensional array is defined in memory to store image data. The first dimension is represented by the variable y, used for horizontal synchronization signal counting; the second dimension is represented by the variable x, used for pixel synchronization signal counting. The basic image acquisition process is as follows: After initializing the OV7620 with SCCB, the interrupt corresponding to VSYNC is enabled. In the Vsync_IRQ() interrupt service routine, it is determined whether a frame of data has been acquired. If yes, data processing is performed in the loop of the main program; otherwise, the interrupt corresponding to HSYNC is enabled, and y is set to 0. In the Hsync_IRQ() interrupt service routine, the valid level of HREF is checked. If valid, y is incremented by 1, x is set to 0, and the interrupt corresponding to PCLK is enabled. In the Pclk_IRQ() interrupt service routine, the valid level of HREF is checked. If valid, z is incremented, and image data of one pixel is acquired simultaneously. 2.3 Image Data Output Speed ​​Matching Among the three synchronization signals of the OV7620, PCLK has the shortest period. When the OV7620 uses a 27 MHz system clock, the default PCLK period is 74 ns. However, the LPC2210's interrupt response time is much longer than this. The LPC2210's maximum interrupt latency is 27 processor instruction cycles, and its minimum latency is 4 instruction cycles. Adding interrupt service time, context recovery time, etc., the time to complete one interrupt response is greater than 7–30 instruction cycles. When the LPC2210 uses its highest system frequency of 60 MHz, its interrupt response time is much longer than 0.2–0.6 μs, so the OV7620's PCLK frequency must be reduced. By setting the clock frequency control register, the PCLK period can be set to approximately 4 μs. 2.4 Image Data Access When the OV7620 operates in master mode, its YUV channel continuously outputs data to the bus. If the YUV channels of the OV7620 are directly connected to the DO~D15 data bus of the LPC2210, it will interfere with the data bus and prevent the LPC2210 from operating normally. If isolation methods such as 74HC244 are used to share the data bus in a time-sharing manner, the system operating speed will be greatly reduced, preventing the LPC2210 from retrieving data from the bus in time, resulting in incomplete image data. Since the LPC2210's data bus width is 32 bits, and Flash and SRAM only occupy the lower 16 data lines D0~D15, the method shown in Figure 1 can be used to set the idle higher 16 data lines D16~D31 as GPIOs for acquiring the 16-bit image data output by the OV7620. 2.5 Image Data Recovery When the OV7620 adopts the 16-bit output mode, the data output format of the Y and UV channels is listed in Table 1. As can be seen from Table 1, each row of the Y and UV channels alternately outputs the repeated data of the previous row and the new data of the current row. Within a single row, B data appears only in odd-numbered columns, and R data appears only in even-numbered columns. The following section uses a 55-pixel array as an example to detail image data recovery. First, a 515-byte array is defined. The image data of 55 pixels is read in the Pclk_IRQ() interrupt service routine. Then, the image data is interpolated. Odd-numbered pixels are stored as B, G, and 0 in three consecutive bytes of the array, while even-numbered pixels are stored as O, G, and R. Finally, the RGB value of the current row is calculated by averaging each byte of the current row with each byte of the corresponding column in the next row. Within each row, the R data for odd-numbered pixels and the B data for even-numbered pixels are obtained by averaging the R and B data of the two pixels on either side of each row. In this way, an image is successfully recovered. The image data can be directly saved as a binary file (this system uses serial port output to the PC for display), or a BMP bitmap file header can be added to save it as a DIB bitmap file with biBitCount=24. The LPC2210 can also be used for further processing of this image data, such as fingerprint recognition. 3. Conclusion The image acquisition speed of this system is mainly limited by the interrupt response time of the LPC2210. Using an ARM chip with a DMA controller and higher processing speed can significantly improve the overall image acquisition system speed. For example, using the S3C2410 with an ARM9 core, its maximum system frequency reaches 203 MHz, and the time to complete one DMA transfer is approximately 30 ns. This is less than the default PCLK period of 74 ns, achieving an image acquisition speed of 30 fps. Compared to image acquisition systems using OV511+ or CPLD/FPGA, this image acquisition system greatly simplifies the system structure, reduces system design costs, and shortens the development cycle. Image data acquisition and processing are both completed by the ARM chip, thus reducing the probability of transmission errors during data transfer and improving system reliability.