Introduction This paper, from a practical application perspective, designs a digital video interface conversion device using an FPGA as the main control chip. This device performs operations such as acquisition, color space transformation, and resolution conversion on ITU-R BT.656 format data generated by the MT9M111 digital image sensor, completing the conversion from ITU-R BT.656 format data to DVI format data. This allows the BT656 format images from the MT9M111 digital image sensor to be displayed on a DVI-I interface monitor in two display formats: 1280×960 (60Hz) and 1280×1024 (60Hz). It also features an image freeze function and achieves low power consumption in standby mode when the system is idle, making it suitable for industrial environments using mobile devices. Overall Scheme Design The process of acquiring and displaying real-world scenes is shown in Figure 1. After the MT9M111 image sensor acquires real-world scenes, it sends the generated ITU-R BT.656 data stream to the video conversion interface through the ITU data output port. The video conversion interface converts the ITU-RBT.656 data stream from the ITU data input port into a TMDS data stream and sends it to the display terminal via the DVI-I port. In this design, the resolution of the MT9M111 output image is 1280×960. [align=center] Figure 1 System Acquisition and Display Process[/align] In the process of acquiring and displaying real-world scenes, the video conversion interface function is implemented through the following steps: 1) Deinterleaving the received ITU-RBT.ITU656 data stream; 2) Performing color space conversion on the deinterleaved data stream; 3) Writing the RGB value of each converted pixel into memory; 4) Reading the RGB value of the pixel from memory and converting it into a TMDS symbol sequence; 5) Reading the RGB value of the pixel from memory and converting it into a VGA analog signal value. Hardware Architecture Design The hardware architecture block diagram of the system is shown in Figure 2. The ITU signals output by the image sensor (including YCbCr data stream, horizontal and vertical sync signals, and pixel clock) are sent to the FPGA main control chip via the ITU input interface. The FPGA main control chip deinterleaves and converts the color space of the ITU signal, then writes the converted RGB values ​​of each pixel into the SDRAM memory. The FPGA main control chip then reads the RGB values ​​of the pixels from the SDRAM memory according to the output resolution requirements, and sends the RGB values ​​to the TMDS transmitter chip and D/A chip according to the VGA timing standard. The TMDS transmitter chip provides the digital channel for video data, and the D/A chip provides the analog channel for video data, both converging at the DVI-I output interface for display on a digital or analog monitor. [align=center]Figure 2 Hardware Architecture Block Diagram[/align] The output image resolution requires a data transmission bandwidth of at least 100 MHz (pixels/second) between the FPGA and the TMDS transmitter chip, thus requiring a sufficiently high FPGA speed. Simultaneously, due to the numerous interconnections between the FPGA and peripheral devices, a sufficient number of pins is required for the FPGA. Furthermore, since the clock frequency provided by the crystal oscillator is 50 MHz, which is insufficient for transmission speeds above 100 MHz, a phase-locked loop (PLL) is required within the FPGA. Additionally, to enable offline system operation, the FPGA must support a configuration chip. Finally, considering the system's footprint and future upgrades, the FPGA's internal resources needed to be as abundant as possible. Therefore, Altera's Cyclone series FPGA was ultimately selected. Since video data storage and display occur simultaneously, and SDRAM is a single-port device, data writing and reading cannot occur concurrently. Therefore, two SDRAMs were required to perform ping-pong operations simultaneously to complete continuous data reading and writing. Micron's MT48LC2M32B2TG-6 SDRAM was ultimately chosen; the Silicon Image SiI164CT64 TMDS transmitter chip was selected. Because the output image resolution requires a data bandwidth of over 100MHz between the FPGA and the TMDS transmitter chip, and this data stream also needs to be fed into a D/A chip for digital-to-analog conversion, the D/A chip's conversion rate needed to be over 100MHz. Furthermore, since the R, G, and B data widths are all 8 bits, a dedicated image D/A chip was required, which needed to have three data channels (R, G, and B), each with a width of at least 8 bits. Based on the above requirements, the system ultimately selected the CSEMIC CSV7123 image D/A chip. FPGA Functional Design: The FPGA, as the system's main control chip, is the core of the software design. According to the overall design concept, the FPGA main control chip's operation process is as follows: First, it receives the ITU-R BT.656 format video data stream from the image sensor. After deinterleaving, the interleaved serial YCbCr values ​​in the pixel data stream are decoupled into independent parallel YCbCr values. Then, the deinterleaved YCbCr values ​​are converted to their corresponding RGB values ​​using color space conversion. Next, these RGB values ​​are stored in an SDRAM memory. Simultaneously, the RGB values ​​of the pixels are read from another SDRAM memory and sent to the TMDS transmitter chip and the D/A chip. After passing through digital and analog channels, the data is transmitted to a DVI or VGA monitor for display. The software functional block diagram designed based on the FPGA main control chip's operation process is shown in Figure 3. [align=center]Figure 3 Software Functional Block Diagram[/align] In Figure 3, the FPGA has two internal operating clocks. Divided by the dashed line, the clock to the left of the dashed line is the 54MHz pixel clock from the image sensor; the clock to the right of the dashed line is a 108MHz clock generated by multiplying the 50MHz crystal oscillator clock via a phase-locked loop. The 108MHz clock is determined by the resolution of the output image. The two clock domains are connected via an asynchronous FIFO. The entire system is divided into six modules: a deinterleaving module, a YCbCr to RGB conversion module, an asynchronous FIFO module, a ping-pong operation module, an SDRAM controller module, and a VGA transmission module. In addition, the system can also implement functions such as image freeze, system standby, and mode selection. Image Display Effect Figure 4 shows the display effect in 1280×960 resolution mode. The video image resolution detected by the monitor in the figure is 1280×960. [align=center]Figure 4 Display effect in 1280×960 mode[/align]