Abstract: This paper introduces a scheme for adding image acquisition functionality to a low-end embedded system. The MT9V011 CMOS digital image sensor is applied to an embedded system based on a low-end Philips ARM7 processor. The system uses a CPLD to read images acquired by the MT9V011 and caches them in memory for subsequent processing. The image acquisition function of the system has been verified on a PC platform. Keywords: CMOS digital image sensor; embedded system; programmable logic device; image acquisition Introduction Currently, in embedded systems, image acquisition can be achieved using analog cameras, CCD image sensors, or CMOS digital image sensors. CMOS digital image sensors are the most widely used due to their high cost-effectiveness and direct output of digital image data. The MT9V011 is such a CMOS digital image sensor. This paper will introduce the application of the MT9V011 CMOS digital image sensor in a low-end ARM7 processor system. Adding an Image Acquisition System to a Low-End Embedded System Real-time image acquisition systems have been widely used in high-end embedded systems such as mobile phones, PDAs, and real-time monitoring systems. In such systems, the processor has the following characteristics: high processing speed to process large amounts of acquired image data in real time; large memory to store several complete frames of image data; and rich peripheral interfaces that allow for easy expansion with large-capacity storage devices such as CF cards and SD cards to back up image data. However, in some measurement and control fields, image acquisition is also required so that managers can intuitively monitor the measured object. Since the changes in the measured object are relatively slow, real-time image acquisition is not necessary; transmitting one image back to the monitoring center every so often is sufficient. In these systems, the processors are mainly designed for the control field, and they are characterized by small memory, slow processing speed, and few peripheral interfaces. Therefore, adding image acquisition functionality to these low-end embedded systems faces the problem of limited processor processing power and hardware resource constraints. Figure 1 shows the working timing of the MT9V011 CMOS camera chip. The MT9V011 CMOS image sensor, based on innovative CMOS active pixel technology, integrates VGA resolution and many superior features not available in CCD. It can output high-quality progressive scan images at frame rates up to 30fps, and its battery life is significantly extended compared to CCD products, making it an ideal choice for USB cameras in mobile phones, PDAs, and PCs. The MT9V011 integrates multiple camera functions (including windowing, line mirroring, horizontal and vertical image flipping, electronic rotating shutter (ERS), and column mirroring) directly onto the chip, reducing the additional components typically required for CCDs and minimizing product size and motherboard space. Its variable functions, such as programmable gain, frame rate, and exposure control, can operate in default mode or be programmed by the end user through a simple two-wire I2C interface. The MT9V011 outputs a 640×480 pixel image by default. The timing diagram of the MT9V011 chip is shown in Figure 1. Here, LINE_VALID is the line valid signal, PIXCLK is the pixel clock signal, DOUT9～DOUT0 are 10-bit image data, and FRAME_VALID is the frame valid signal. The LINE_VALID period has 640 PIXCLK clock cycles, and the FRAME_VALID period has 480 valid LINE_VALID signals. By default, image data is output sequentially from the first row and first column, on the rising edge of the PIXCLK signal. The MT9V011 outputs images in RGB Bayer format. System Design Scheme This image acquisition system is based on Philips' low-end ARM7 embedded microprocessor LPC2104, and the CMOS camera chip uses Micron's MT9V011. The MT9V011's maximum image output rate is 30fps, while the LPC2104 processor's I/O port read/write speed is far from sufficient. By repeatedly setting one of its I/O ports high and then low, the output square wave frequency does not exceed 4MHz. Furthermore, the amount of image data transmitted is too large for resource-constrained embedded systems. The MT9V011 outputs a single image of 300KB by default, while the LPC2104 processor has only 16KB of memory and lacks an open memory expansion bus, making external memory expansion inconvenient. Other low-end control processors such as AVR and MCS51 microcontrollers also face similar issues. However, due to their high cost-effectiveness, ease of development and debugging, and ability to quickly build application systems, they are widely used in many fields. To address the resource and performance limitations of these processors, auxiliary measures can be taken. Programmable logic devices (PLDs) offer advantages such as high processing speed and in-system programming capabilities, making them well-suited for combining with these low-end processors to solve problems that pure processor systems cannot handle. With the development of PLD technology and related advancements, such systems are becoming increasingly widely used. This paper employs this approach to solve the problem of image acquisition that a single processor cannot accomplish. Specifically, a PLD interfaces with the MT9V011, controlling the image data to be buffered in SRAM, and then instructing the processor to read the data. This simultaneously solves the problems of slow processor I/O transfer speed and insufficient memory, enabling the system to be built and complete the image acquisition function. The image acquisition system block diagram is shown in Figure 2. The system consists of four main parts: a CMOS camera circuit, a camera buffer control logic circuit, an SRAM memory, and a 32-bit embedded system bus interface. The system's camera buffer control logic circuit is implemented by a CPLD EPM7128S. Figure 2: Embedded Image Acquisition System Block Diagram - CPLD Control Logic Design Due to limitations in I/O transfer rate and memory, the system's main processor, LPC2104, cannot complete the function of acquiring and storing images. Therefore, it is necessary to use an additional CPLD chip to assist in completing the system function. The control logic circuit within the CPLD chip completes the function of reading image data and buffering it into SRAM. Because the system does not perform real-time image acquisition and processing, the input clock can be changed to reduce the output image rate of the CMOS digital image sensor. The CPLD clock in the system uses 40MHz, and the clock frequency divided by 10 is used as the clock for the CMOS image sensor. This reduces the image output rate, alleviating the processor's burden of image data processing and allowing it free time for other control operations. Since the CPLD needs to read image data from the CMOS image sensor and cache it in SRAM, the CPLD's on-chip logic is primarily written based on the timing of the image sensor's output data and the SRAM's read/write timing. The CPLD's on-chip control logic circuit is mainly implemented using a state machine written in Verilog. Additionally, there are some additional gate circuits, multiplexers, and adders, which, together with the state machine, form the system's camera cache control logic circuit. The CPLD control logic flowchart is shown in Figure 3. Figure 3 CPLD Control Logic Flowchart Functional Verification To verify the system's image acquisition function, the data cached by the CPLD needs to be processed and displayed. Since PCs have abundant hardware and software resources, this paper utilizes a PC to display images and verify the correctness of the image acquisition function. Specifically, the system's main processor, LPC2104, reads image data from SRAM and transmits it to the PC via serial port. Software is written on the PC to receive the data and perform simple processing, allowing the image to be displayed on the PC screen, thus verifying the system's functionality. Conclusion This paper implements image acquisition functionality by adding a CMOS digital image sensor to a low-end embedded processor system and writing hardware description language and embedded processor programs. The paper presents a solution for adding image acquisition functionality to a low-end embedded system. This solution has advantages such as high cost-effectiveness and strong versatility, and can be widely applied to various monitoring systems based on low-end embedded processors, enabling monitoring managers to intuitively understand the monitored objects. This solution can also be further extended to implement many functions, such as image comparison and image recognition. References: 1. Zhou Ligong et al., eds. ARM Microcontroller Fundamentals and Practice. Beijing University of Aeronautics and Astronautics Press. 2005.8 2. Li Xianyong, ed. Visual C++ Serial Communication Technology and Engineering Practice. People's Posts and Telecommunications Press. 2002.5