[b]1 Introduction[/b] With the continuous development of information processing technology, especially the widespread application of computers and the rapid development of the Internet, the reliability requirements of power supply systems are getting higher and higher, and therefore the requirements for uninterruptible power supply (UPS) technical indicators are also getting higher and higher. The core part of UPS is a constant frequency and constant voltage inverter. Due to the need for a large number of discrete components in traditional analog control, aging and temperature drift seriously affect the long-term stability of the system. DSP-based digital control technology can greatly improve the consistency of products, while increasing the flexibility of control and improving the stability and reliability of the entire system[1]. This paper mainly proposes a digital control UPS inverter structure and discusses the parameter design of the control system in detail. [b]2 System Structure[/b] Figure 1 is the block diagram of the digital control UPS inverter proposed in this paper. The main circuit adopts a full bridge structure, and the control circuit is a fully digital controller with the TMS320F240 DSP chip for motor control from TI as the core[2]. Lf and Cf are the output filter inductor and filter capacitor of the inverter, and rL and rC are the series parasitic resistances of the filter elements, respectively. Considering the accuracy of control and the cost of the product, the control system adopts a system control method with resistor sampling and common ground between the main power circuit and the control circuit. Rs1 and Rs2 are output voltage sampling resistors, and Rc is inductor current sampling resistor. The voltage and current sampling signals are input to the A/D conversion port of the DSP through the sampling network. The PWM module of the DSP outputs 4 PWM signals and drives 4 IGBT transistors after passing through the drive circuit. [b]3 Control System Design[/b] 3.1 Digital Dual-Loop Controller Structure There are many schemes for the control of inverters[3]. The UPS inverter in this paper adopts the digital dual-loop PI control method of inductor current mode. The specific inverter digital control block diagram is shown in Figure 2. The dashed box in the figure is divided into the main circuit of the inverter. Vref is the sine wave data table stored in the DSP program space, and VAB is the voltage between the midpoints of the two arms of the inverter bridge. In order to suppress the high-frequency noise in the feedback quantity and improve the sampling accuracy, a resistor-capacitor low-pass filter is added to the feedback channel. The voltage error signal, after being regulated by a digital PI converter, is used as the command for the current loop. The current error signal is then proportionally regulated to obtain the current loop output. The current loop output is compared with the triangular wave generated by the timer to obtain four gate pulses. 3.2 Current Loop and Voltage Loop Parameter Design Figure 3 shows a simplified block diagram of the inner current loop. Zoh is a zero-order hold circuit, and its s-domain transfer function is: where Ts is the sampling period. The voltage and current sampling periods designed in this paper are both 50μs. The open-loop pulse transfer function of the current loop is: The voltage and current sampling periods designed in this paper are both 50μs. The open-loop pulse transfer function of the current loop is: Since the tracking speed of the current inner loop designed above is much faster than that of the voltage outer loop, the following reasonable simplification is made when designing the voltage outer loop: Assume that the inductor current can already track the command current. Therefore, the current inner loop can be assumed to be a unit proportional element 1, thus obtaining the open-loop pulse transfer function of the voltage outer loop as: Similarly, according to the deadbeat control principle, setting the characteristic root to 0, K1 can be any constant. K1 can be determined based on the relationship between K1 and K2 and combined with simulation methods. In the above control parameter design process, a simplified block diagram with unit feedback was used. The actual circuit feedback channel will definitely have a proportional element. Therefore, based on the above design, the control block diagram needs to be transformed according to the actual feedback proportional to obtain the final control loop parameters.　　3 Sampling Control Timing Design Figure 5 is a schematic diagram of the sampling control timing proposed in this paper. t0-t4 is one switching cycle. Due to the use of the frequency-doubling unipolar sinusoidal pulse width modulation method, the pulsation frequency of the output filter inductor is twice the switching frequency, which can reduce the size of the filter element. At time t1 when the timer cycle is interrupted, two A/D converters are started simultaneously to sample the voltage and current feedback. At time t2, the A/D conversion ends, and the dual-loop control algorithm is executed immediately until time t3. At time t4 when the timer underflow is interrupted, the calculated comparison value CMPRx is loaded. Obviously, in this sampling control method, the control point is only delayed by half a switching cycle relative to the sampling point. Compared with the sampling control method with a delay of one switching cycle reported in many literatures [4][5], the real-time performance of the control is greatly improved. Simulation and experiment have verified this. [b]4 Simulation and Experiment Results[/b] Table 1 lists some of the main parameters of the digital control inverter proposed in this paper. Before conducting the actual experiment, the UPS inverter system was simulated using the MATLAB SIMULINK toolbox. Figure 6 shows the simulated waveforms of the output voltage and load current during load switching. Figure 7(a) shows the steady-state experimental waveforms of the output voltage and inductor current under full load of 3kVA. The THD was measured to be 1.4% using a LEM clamp meter HEMEANALYST2060. The experimental data shows that the control system has good steady-state characteristics. Figure 7(b) shows the experimental waveforms of the load voltage and load current during the half-load to full-load switching, and Figure 7(c) shows the switching from full load to half load. The experimental waveforms match the simulated waveforms well, showing that the inverter can quickly adjust the output voltage to a steady state, indicating that the control system has good dynamic characteristics. [b]5 Conclusion[/b] Compared with analog control technology, the DSP-based all-digital control technology greatly simplifies the design of the control circuit and increases the flexibility of control. At the same time, the adoption of digital deadbeat control technology and sampling control method with a delay of half a switching cycle greatly improves the dynamic characteristics of the inverter. Simulations and experiments both verified the advanced nature and practicality of this DSP-based all-digital control scheme. Editor: He Shiping